Describe Details
The SOI silicon wafer (Silicon-On-Insulator) is an advanced three-layer semiconductor substrate architecture consisting of a top device-quality silicon layer, a buried oxide (BOX) insulating layer, and a bottom handle silicon wafer substrate. Our SOI silicon wafer portfolio covers 4-inch to 8-inch diameters with both Bonded SOI (BESOI) and SIMOX structure options available to meet diverse application requirements for advanced semiconductor devices that demand performance beyond conventional bulk silicon capabilities.
Our BESOI SOI silicon wafer is manufactured through wafer bonding and smart-cut technology, where two polished silicon wafers are bonded together with an oxide layer interface, followed by precise thinning of the top layer through grinding and polishing to achieve exact device silicon thickness specifications. The SIMOX SOI silicon wafer is produced via high-dose oxygen ion implantation deep into the silicon substrate followed by high-temperature annealing, forming a continuous buried oxide layer beneath the remaining surface silicon layer. Both technologies deliver the signature SOI advantages including dramatically reduced parasitic capacitance, lower power consumption, complete device isolation without junction leakage, elimination of latch-up effects, and improved radiation hardness compared to conventional bulk silicon substrates.
We offer fully customizable SOI silicon wafer specifications including top silicon thickness ranging from tens of nanometers to several micrometers, buried oxide layer thickness from 100nm to 2 micrometers, and various handle wafer resistivity and doping options. The top device layer can be supplied as polished ready for processing or with additional epitaxial growth, with doping type and resistivity precisely tailored to customer device design requirements. Each SOI silicon wafer undergoes comprehensive characterization including thickness mapping through spectroscopic ellipsometry, crystal quality verification through X-ray diffraction, surface defect inspection using optical scanning, and BOX layer integrity testing to ensure device-grade quality throughout the substrate.
The SOI silicon wafer enables significant performance improvements in high-speed RF devices, power electronics, automotive integrated circuits, MEMS sensors, radiation-hardened aerospace components, and advanced CMOS manufacturing. As a specialized SOI silicon wafer supplier, we work closely with customers to develop custom specifications and maintain consistent quality control throughout the production process, delivering advanced substrates that enable next-generation semiconductor device performance for our global partners in fabless design, foundry manufacturing, and university research institutions. We provide comprehensive characterization reports with every shipment and offer technical consultation for customers transitioning from bulk silicon to SOI-based device designs. Our technical team also provides process integration consultation services to help customers optimize their device designs and manufacturing processes when adopting SOI technology, ensuring a smooth transition from concept to production.
| Parameter Category | Specifications |
|---|---|
| Wafer Diameter | 4 inch to 8 inch |
| SOI Structure Type | Bonded SOI (BESOI), Separation by Implanted Oxygen (SIMOX) |
| Top Silicon Thickness | 50 nm to several micrometers, customizable |
| Top Silicon Uniformity | ≤ ±5% |
| Top Silicon State | Polished state or epitaxially grown state |
| Buried Oxide (BOX) Thickness | 100 nm to 2 μm, optional |
| BOX Layer Quality | Excellent oxide integrity, low defect rate |
| Handle Substrate Material | CZ or FZ silicon wafer (optional) |
| Substrate Resistivity | Customizable |
| Doping Type & Resistivity (Top Silicon) | Customized per device requirements |
| Crystal Orientation | Mainly <100>; special orientation customization supported |
| Full Inspection Process | Multi-point thin film thickness measurement, crystal quality inspection, surface defect scanning, BOX breakdown voltage test (per wafer) |
| Key Features | Low parasitic capacitance, low power consumption, complete device isolation, strong radiation tolerance, latch-up elimination |
| Applications | RF power devices, high-voltage power ICs, automotive electronics, MEMS sensors, aerospace radiation-hardened devices, advanced CMOS process R&D |
| Technical Support | Customized technical support; special specification development available upon request |
FAQ
Yes.
Yes, we can label the products according to your requirements. Both internal and external labels are acceptable.
Yes, we have a factory in Jiangsu. Welcome to visit our company and factory.
Our main focus is on the product process and production cycle.
Based on your needs, we will arrange for same day shipment for items in stock, and for items out of stock, we will check the delivery date. Delivery will be made within the delivery time.