EPI Wafer

Epitaxial wafer (EPI) refers to the semiconductor thin film grown on a substrate, which mainly consists of three parts: P-type layer, quantum well and N-type layer. Gallium nitride (GaN) is the mainstream epitaxial material at present, while common substrate materials fall into three categories: sapphire, silicon and silicon carbide. The quantum well generally adopts a 5-period structure. Metal-Organic Chemical Vapor Deposition (MOCVD) is the dominant manufacturing process. As the core segment of the LED industry, MOCVD technology requires sophisticated technical expertise and substantial capital investment.

Ordinary epitaxial layers, multi-layer structured epitaxial layers, ultra-high-resistivity epitaxial layers and ultra-thick epitaxial layers can all be fabricated on silicon substrates. The resistivity of the epitaxial layer can exceed 1,000 Ohm-cm, with a wide range of conductivity types available, including P/P++, N/N++, N/N+, N/N+/N++, N/P/P and P/N/N+.

Silicon epitaxial wafers serve as core raw materials for manufacturing a wide spectrum of semiconductor devices, and are widely applied in consumer electronics, industrial electronics, military electronics and aerospace electronics.
Silicon-on-Sapphire (SOS) technology is essentially a heteroepitaxial process, wherein a thin silicon film (typically thinner than 0.6 μm) is grown on sapphire wafers. SOS falls under the silicon-on-insulator (SOI) epitaxy technology family for CMOS devices. Thanks to its inherent radiation resistance, SOS is primarily deployed in aerospace and military electronic applications.
High-purity synthetic single-crystal sapphire is the standard substrate material. The silicon thin film is fabricated by thermally decomposing silane, followed by silicon deposition onto the sapphire substrate.

The key advantage of SOS lies in its superior electrical insulation performance, which effectively blocks radiation-induced stray current leakage to adjacent components. However, commercial mass adoption of SOS remains far from realization, as it cannot be well adapted to high-density modern transistor manufacturing. This limitation stems from lattice mismatch between silicon and sapphire, which generates dislocations, twins and stacking faults during the SOS epitaxial process. Additionally, silicon layers near the substrate interface suffer aluminum contamination diffusing from the sapphire substrate.